Hardware emulators are programmable devices used in the verification of hardware designs. Hardware emulators may include hardware components capable of processor-based (e.g., hardware-based) emulation of logic systems, such as application specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), and the like. By executing various forms of programmable logic, the hardware emulators may be programmed to mimic the functionality of nearly any prototype logic system design such as an integrated circuit, an entire board of integrated circuits, or an entire system that is undergoing testing. This mimicking of functionality allows logic system designers to prototype their logic system design using processor-based emulation before actually manufacture the logic system, such as an ASIC product, thereby potentially saving millions of dollars by avoiding design failures.
A hardware emulator may be comprised of multiple processors. These processor-based emulators sequentially evaluate combinatorial logic levels, starting at the inputs and proceeding to the outputs. Each pass through the entire set of logic levels is known as a cycle, and the evaluation of each individual logic level is known as an emulation step. During each process cycle, each processor is capable of emulating a logic gate, mimicking the function of a logic gate in an integrated circuit. The processors are arranged to compute results in parallel, in the same way logic gates present in an integrated circuit compute many results in parallel. This creates a chain of logic similar to what occurs in an integrated circuit. In the chain of logic, efficient communication between processors is crucial.
The programs executed by the processors in a hardware emulator may include instructions containing a sequence of operations. The processor typically corresponds to an instruction memory that is read sequentially and provides instructions that are used to read bits out of a data array. Each processor is connected to the data array that is a special memory, and has multiple read ports and supplies input data to the processor via each read port. The processor evaluates the data supplied from the data array in accordance with an instruction word supplied from an instruction memory. The processor does not always require input data from all of the read ports of the data array. The bits that are read from the data array are then fed to a lookup table (LUT) that is controlled by the instruction, and the result of the LUT function is then stored back into the data array. The data array also contains the results of previous LUT evaluations. The data array may also store inputs that come from outside the processor (from other processors of the hardware emulator), and therefore the LUT not only has access to all previous results, but also values from outside the processor.
The data array stores outputs of the processor for an emulation cycle (in a single phase) and serves as the inputs to the processor. The data value produced by the processor may then be written to the data array at an address indicated by a step number of a current instruction. For example, a result of the instruction executed at step 100 is stored in the data array at address 100. Currently, the processor outputs are written every step in the data array even if the processors did not do any useful computation. For example, in a design with an emulation cycle that has 500 steps, a processor may produce only 200 useful outputs, but due to the current configuration, the data array must do 500 writes of the processor outputs although only 200 are really needed. Because of this existing configuration, there is a waste of memory space of the data array as well as power since the outputs that are not useful are also being written into the data array.
Thus, there is a need in the art for a hardware emulator having improved space utilization of the data array.